Verilog-A Modeling
Yakka Design has extensive experience in Verilog-A modeling both at the block and system level. At the block level we have used Verilog-A to create complex inputs and to stop simulations when certain conditions are reached. We have also used Verilog-A to module subcircuits. This decreases the simulation time which allows more simulations to be ran.

At the system level we have written abstract views of analog blocks to allow system level simulations to complete in a reasonable amount of time. We also have experience running mixed signal simulations with Verilog, Verilog-A, and transistors.


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